ABOUT / 00
Designed and engineered, artfully — silicon to software.
I build systems where the constraints are real: timing, determinism, correctness you prove rather than assume. I like turning physics-grounded models into instrumented, testable algorithms, and I learn at the hardware–software boundary — from FPGA RTL closed on real silicon to low-latency Rust and C++.
That instinct shows up across quantitative finance, drones & music tech, and motorsport, but the work underneath is the same: make it fast, make it correct, make it real-time.
TIMELINE
- 2022–2026
- BSc Computer Science, University of Manchester (2022–2026) — hardware track: SoC design, processor microarchitecture, multicore computing, computer architecture, microcontrollers, digital logic + Verilog.
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- Jun–Aug 2025
- AI / Software Engineering Intern, CarrLane Manufacturing (Chennai).
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- Sept 2026–2028
- MSc Computer & Embedded Systems Engineering (CESE), TU Delft (Sept 2026–2028).
SKILLS
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- HDL & EDA
- SystemVerilog, Verilog, Vivado (Artix-7/Spartan-7), Xilinx ISE (Spartan-6), ModelSim/Questa, register-mapped peripherals
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- Languages
- Rust, C++17/20, C, Python, RISC-V & ARM assembly
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- Numerics & Control
- RK4, CasADi/IPOPT MPC, Kalman filtering, differential flatness
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- Concurrency & Systems
- pthreads, std::thread, OpenMP, atomics, spinlocks, NUMA affinity, tokio async
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