01

Quantitative Finance

Low-latency systems across the hardware/software boundary: a relation-typed trading research stack, FPGA RTL closed on real silicon, a RISC CPU, and measured parallelism.

RESEARCH

01

Quant Trading System (Automaton-QTS)

A multi-signal trading engine, an agent-based market simulator, and a relation-typed contagion-propagation graph that I proved is dead in equities and alive in crypto.

  • Python
  • PyTorch
  • torchdiffeq
  • NautilusTrader

EMBEDDED HARDWARE

01

Cellular-Automaton SoC Accelerator

A from-scratch SystemVerilog drawing unit that renders Wolfram cellular automata — programmable rule as a pure lookup, LFSR-seeded, taken through Vivado to an Artix-7 and demoed live on a monitor.

  • SystemVerilog
  • Vivado
  • Artix-7
  • RISC-V assembly
case study
02

Stump — 16-bit RISC CPU closed on Spartan-6 silicon

A multi-cycle 16-bit RISC processor built bottom-up from RTL primitives in Verilog, then synthesised, placed-and-routed, and timing-closed on a real Spartan-6 at 98% slice occupancy — the first design I carried through the full FPGA back-end flow.

  • Verilog-2001
  • Xilinx ISE
  • Spartan-6 (xc6slx4)
  • ModelSim
case study

SYSTEMS

01

Multicore Computing Labs

Three parallelism labs on a 72-core 2-socket NUMA machine — a 132× temporal-blocking Jacobi stencil, a 30.7× NUMA-aware vecadd, and dining philosophers scaling near-linearly to 1.04M meals/s.

  • C
  • C++20
  • pthreads
  • OpenMP
case study

NEXT / WHAT I'D BUILD

  • Fixed-point / integer-tick pricing (today everything is float)
  • A price-time-priority limit-order-book matching engine
  • Hand-written SIMD and a lock-free SPSC ring buffer